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In Reply to: RE: Absolute Sound on Auralic Vega PLL posted by soundchekk on February 17, 2015 at 00:26:17
if he thinks this, then he doesn't know what he is on about. The usual lock range for a run of the mill PLL is 400 to600 ppm. A tight PLL for lower jitter can be 100 or even 50ppm in the extreme case.
Follow Ups:
"if he thinks this, then he doesn't know what he is on about. The usual lock range for a run of the mill PLL is 400 to600 ppm. A tight PLL for lower jitter can be 100 or even 50ppm in the extreme case."
You just don't get it at all. All you are doing by continuing to make posts is to demonstrate your arrogance and your ignorance. You may not realize it, but you telling people they don't know what is about, when these people know this technology inside and out by virtue of having extensive experience designing and building things from the ground up.
The SPDIF input on the ESS chip oversamples the Manchester code. This enables it to achieve bit lock on the input data stream, regardless of the incoming sample rate. There is no center frequency at all. No question of tolerances, etc.. Just so that the master clock is sufficiently faster than the sample rate.
If the SABRE chip is run in the mode with ASRC enabled, which is what I was discussing, then the SABRE chip provides a sample rate conversion from the average incoming sample rate to the fixed master clock sample rate. The way this is done is described in the SABRE white paper. Basically, there is a digital phase lock loop. This makes it possible to have a very narrow bandwidth on the frequency, starting with a wide bandwidth at first to get a quick lock and then narrowing it down once the average input sample rate has been determined. The lock range adapts to the properties of the input signal.
You will also see that the SABRE data sheets do not list specific sample rates or clock tolerances. None of this is given because none of this is necessary. If you want more details on how this works, in addition to the white paper there are patents that are easy to find. Frankly, I doubt you have the knowledge or ability to understand this stuff. If you did, you would not be making the posts that you make.
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
in the Auralic? Please don't speak from ignorance of how this has been done. As I pointed out, you haven't seen the schematic and you are just exhaling hot air.
"How do you know that the standard ESS feature is in the Auralic?"
All this was explained in my original post. I will repeat what I wrote, verbatim.
"There may be serious problems with the Vega's's design, but no blame can rest on ESS. The SABRE chip will lock onto any sample rate up to a maximum limit, there is no need for any accuracy at the source. If the DAC designer chooses to disable this feature then he is on his own and must keep all of his clocks synchronized, provide his own PLL, etc..."
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
It's your unjustified and slanderous accusations about the design of the Auralic that I have been talking about. If you want to talk about spdif in the ESS, then this is your tune alone.The usb card is likely to output I2S to the chip. How Bck, LRCK and Serial Data are transferred, timed, and relocked (or not), and how this relates to the ESS's oven precision clock cannot be determined without the circuit diagram. To speculate the way that you have done is simply not professional.
We do know that there is a lock issue; is it the computer, or is it the dac?. You blame the dac. I said that this could equally be the computer and or the software. We know that the dac in exact mode works with clean Windows machines. We also know that, by resampling in software in this particular machine, the dropouts are much reduced. So, which is the more reasoned way to examine the issue? Your 'treatise' on the ESS, it's spdif, or my attempts to help resolve the issue?
Incidentally I have a lot of experience with various input formats on the ESS9018, which I built sometime ago.
Edits: 02/19/15
"Whoss talking about ESS being at fault?"
You were. It was your off-base comment that started my posting on this subject:
"It supports the suggestion, that it is the ESS master clock lock range that is at play with lock on issues with MAC computers running some player software."
I suggest you listen to what Gordon has to say. Not only does he understand the issues in general as I do, he understands them in depth, having designed and implemented products that implement the Async USB protocol. You, on the other hand, are not able to even manage receipt and filtering of email messages on your own computer, let alone understand the design and implementation of computer protocols.
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
misdirect words away from the meaning of a post. ESS clock means clock(s) relating to the operation of the Auralic's ESS chip. This is not just spdif but Bck LRck etc etc.Gordon? He sends me an email not knowingly my email address!!!!!
Edits: 02/19/15
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