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In Reply to: RE: Absolute Sound on Auralic Vega PLL posted by Tony Lauck on February 15, 2015 at 10:25:34
"there is no need for any accuracy at the source"
This is not correct Tony. I've and 1000s others have been playing around with several DIY ESS Sabre modules for quite some time.
You got fooled by ESS marketing phrases my friend.
No matter how you change the quality of input data. The Sabre will tell you.
Enter the DIY scene and you'll start looking differently at many things.
Follow Ups:
if he thinks this, then he doesn't know what he is on about. The usual lock range for a run of the mill PLL is 400 to600 ppm. A tight PLL for lower jitter can be 100 or even 50ppm in the extreme case.
"if he thinks this, then he doesn't know what he is on about. The usual lock range for a run of the mill PLL is 400 to600 ppm. A tight PLL for lower jitter can be 100 or even 50ppm in the extreme case."
You just don't get it at all. All you are doing by continuing to make posts is to demonstrate your arrogance and your ignorance. You may not realize it, but you telling people they don't know what is about, when these people know this technology inside and out by virtue of having extensive experience designing and building things from the ground up.
The SPDIF input on the ESS chip oversamples the Manchester code. This enables it to achieve bit lock on the input data stream, regardless of the incoming sample rate. There is no center frequency at all. No question of tolerances, etc.. Just so that the master clock is sufficiently faster than the sample rate.
If the SABRE chip is run in the mode with ASRC enabled, which is what I was discussing, then the SABRE chip provides a sample rate conversion from the average incoming sample rate to the fixed master clock sample rate. The way this is done is described in the SABRE white paper. Basically, there is a digital phase lock loop. This makes it possible to have a very narrow bandwidth on the frequency, starting with a wide bandwidth at first to get a quick lock and then narrowing it down once the average input sample rate has been determined. The lock range adapts to the properties of the input signal.
You will also see that the SABRE data sheets do not list specific sample rates or clock tolerances. None of this is given because none of this is necessary. If you want more details on how this works, in addition to the white paper there are patents that are easy to find. Frankly, I doubt you have the knowledge or ability to understand this stuff. If you did, you would not be making the posts that you make.
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
in the Auralic? Please don't speak from ignorance of how this has been done. As I pointed out, you haven't seen the schematic and you are just exhaling hot air.
"How do you know that the standard ESS feature is in the Auralic?"
All this was explained in my original post. I will repeat what I wrote, verbatim.
"There may be serious problems with the Vega's's design, but no blame can rest on ESS. The SABRE chip will lock onto any sample rate up to a maximum limit, there is no need for any accuracy at the source. If the DAC designer chooses to disable this feature then he is on his own and must keep all of his clocks synchronized, provide his own PLL, etc..."
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
It's your unjustified and slanderous accusations about the design of the Auralic that I have been talking about. If you want to talk about spdif in the ESS, then this is your tune alone.The usb card is likely to output I2S to the chip. How Bck, LRCK and Serial Data are transferred, timed, and relocked (or not), and how this relates to the ESS's oven precision clock cannot be determined without the circuit diagram. To speculate the way that you have done is simply not professional.
We do know that there is a lock issue; is it the computer, or is it the dac?. You blame the dac. I said that this could equally be the computer and or the software. We know that the dac in exact mode works with clean Windows machines. We also know that, by resampling in software in this particular machine, the dropouts are much reduced. So, which is the more reasoned way to examine the issue? Your 'treatise' on the ESS, it's spdif, or my attempts to help resolve the issue?
Incidentally I have a lot of experience with various input formats on the ESS9018, which I built sometime ago.
Edits: 02/19/15
"Whoss talking about ESS being at fault?"
You were. It was your off-base comment that started my posting on this subject:
"It supports the suggestion, that it is the ESS master clock lock range that is at play with lock on issues with MAC computers running some player software."
I suggest you listen to what Gordon has to say. Not only does he understand the issues in general as I do, he understands them in depth, having designed and implemented products that implement the Async USB protocol. You, on the other hand, are not able to even manage receipt and filtering of email messages on your own computer, let alone understand the design and implementation of computer protocols.
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
misdirect words away from the meaning of a post. ESS clock means clock(s) relating to the operation of the Auralic's ESS chip. This is not just spdif but Bck LRck etc etc.Gordon? He sends me an email not knowingly my email address!!!!!
Edits: 02/19/15
I thought it clear what I wrote. It is certainly possible to use the SABRE chips in a way that they require accurate clocks, but if the ASRC is used correctly they will lock on to inaccurate sample rates. The on-chip SPDIF receiver logic will still have some limits on signal jitter, measured well into the nanoseconds, because there has to be an open eye pattern. It is certainly possible to botch a design and get terrible signal integrity.
I'm not surprised that DIYers have trouble making the chip work. Apparently even some manufacturers have this problem as well. (I am talking about making it work, not sound good. That's another question entirely, because of the 100 Mhz clock circuitry involved.)
I know how these decoders work. I've designed and implemented them in the past, albeit at much lower signaling rates and clock speeds. But you're right: the SABRE chip documentation is somewhat cryptic. I assume you read and understood the white paper and also the various patents. Were I to design a product around this chip the first thing I would do would be to play with the chip on a bread board and discover how it really works. This is a huge PITA. Back in the day I was designing circuits and software to decode comms data I had access to the actual logic diagrams of the hardware and additional details, such as clock tolerances. I don't DIY, because I was used to working with a fully equiped hardware lab and access to all documentation. But I can see that people will run into problems if they get over their head.
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
''don't DIY, because I was used to working with a fully equiped hardware lab''This is not a reasoned statement. You don't do it because you don't want to.
On the issue of PLL, you are out of your knowledge or comfort zone.
Edits: 02/18/15
Fred,
I see no point in playing with inadequate tools. I don't have the space to set up a proper hardware lab and the test equipment needed would cost more than my audio system.
Have you fixed your scope yet?
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
I don't DIY, because I was used to working with a fully equiped hardware lab and access to all documentation. But I can see that people will run into problems if they get over their head.
Phew. Where's Molière when we need him?
Ever tried reading this (and other such stuff of yours in like vein) in front of the mirror before posting it here? Go on. Give it a try.
D
Par ma foi ! il y a plus de quarante ans que je dis de la prose sans que j'en susse rien, et je vous suis le plus obligé du monde de m'avoir appris cela.
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
il y a plus de quarante ans que je dis de la prose sans que j'en susse rien
Yeah, yeah, I'd guessed you'd know your Molière (and your Google). It was your magnificent, almost magisterial, pomposity I was drawing attention to. This is a hobbyists' forum FFS - let's lighten up a bit.
Go on - you know you can do it.
D
Read that in high school French class over half a century ago. Connection to Richard Strauss came later.
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
Hmmh. I havn't seen any Sabre implementation DIY or commercial, which
really worked well without putting in major effort in front of the DAC.
I read all the flashy promises about that chip. That's why I bought it too.
No question. If well implemented the Sabre chips sound really good. I do have a problem with the marketing message around the "patended Hyperstream" feature.
Cheers
The "patented Hyperstream" feature refers to the sigma-delta modulator. See the White Paper. There was also a video one of the designers gave on this subject. Interesting, because there were artifacts that some audiophiles heard that the designers didn't and that didn't show up on the measurements. As a result there were further improvements made in the modulator, presumably in the chip.
The biggest design challenge with the chip is the very high clock rate and the necessity to have very careful PC board layout and power for the chip and associated clock circuitry. I suspect this is one place where many designs go wrong. However, there are still some issues with the chip that require work around to get the best sound.
First, the ASRC needs to be bypassed, assuming the clock problems can be handled elsewhere. It's better than other ASRCs but it is not a complete solution since it is not bit transparent. At the very least, there is cross talk (admitted in the white paper) from the SPDIF input circuitry that makes it through the chip via ground bounce, etc., and pollutes the analog output. So even though "all" jitter may be removed by the ASRC there will still be input effects.
Second, the upsampling filters (particularly for Red book) are poor, just like almost all filters built into DAC chips. These need to be effectively bypassed by upsampling elsewhere, either in the DAC itself or in the computer. I upsample in the computer, e.g. to 176.4 or 192 before sending PCM to my Mytek. There are much better filters that can be selected, either by system balancing or (better) by adjusting to music genre or individual recording.
Third, the Hyperstream modulator is not as good as it might be. Many people have found that using Miksa's HQPlayer modulator to convert to DSD128 produces better sound than sending high rate PCM to a SABRE chip based DAC, such as my Mytek. Miksa claims he has some spectrum plots that show that his modulator has lower distortion, but I've not seen them. Unfortunately, Miksa's modulator is very compute intensive and some people may find their CPU speed to be a limiting factor.
This is just my personal take on this, and I have attempted to reach conclusions based on improvements when using my Mytek Stereo192-DSD DAC. There were a number of other tweaks that were needed to get around limitations of this DAC, especially bypassing the analog volume control circuitry and using the internal jumpers to reduce the output voltage. This enables me to go direct via balanced XLR to my amplifiers while needing very little digital volume reduction in the ESS chip, i.e. no bits in the input signal are lost at the settings I use for playback.
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
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