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In Reply to: RE: PLLXO question related to LDRse posted by JBen on February 26, 2012 at 12:56:15
You have to consider/include 'everything' when designing PLL's. :) Even interconnect capacitance might be an issue.
You can measure output resistance of a source fairly easily. Take a voltage measure unloaded and also with a 1k resistor attached.
Rout = 1000 times (Ropen-Rload)/Rload
You'd be surprised how high the source resistance is on many components.
Cheers,
Dave.
Follow Ups:
Shouldn't that be Z = 1000*(Vload-Vopen)/Vopen?
On the violin: "Heaven reward the man who first hit on the idea of sawing the innards of a cat with the tail of horse."
So is it's OK to place the pot after the PLLXO? I'm thinking of a dual deck (4 channel) stepped unit.
Edits: 02/26/12
Thanks Davey! Where do I find the impact relative to changes in Rout in a given configuration?
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