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In Reply to: RE: PLLXO question related to LDRse posted by neolith on February 26, 2012 at 11:10:30
Neo, I may have failed to realize this. It could mean that my UBS DAC and the pre-amp have the same output impedance, which I don't know for a fact. I can plug into each separately and measure no change in xover points.
I never saw a spec call for it while designing the PLLXO filters and simply assumed that input impedances was all I had to worry about.
Well, time to start lining up the active stage ducks, then. It was in that "future projects limbo" for when a proper subwoofer integration became a need anyway.
Follow Ups:
You have to consider/include 'everything' when designing PLL's. :) Even interconnect capacitance might be an issue.
You can measure output resistance of a source fairly easily. Take a voltage measure unloaded and also with a 1k resistor attached.
Rout = 1000 times (Ropen-Rload)/Rload
You'd be surprised how high the source resistance is on many components.
Cheers,
Dave.
Shouldn't that be Z = 1000*(Vload-Vopen)/Vopen?
On the violin: "Heaven reward the man who first hit on the idea of sawing the innards of a cat with the tail of horse."
So is it's OK to place the pot after the PLLXO? I'm thinking of a dual deck (4 channel) stepped unit.
Edits: 02/26/12
Thanks Davey! Where do I find the impact relative to changes in Rout in a given configuration?
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