In Reply to: What are you talking about?...... posted by Alex Peychev on January 22, 2004 at 08:33:52:
The 33.8688Mhz is really used by the sample rate converter AD1895A as system/processor clock for processing the 44.1Khz I2S data from the motherboard to the AV Board.
Initially, they really wanted to run the DAC for SACD/non-upsampled CD in 16.9344Mhz, off the 33.8688Mhz/2, so that they can get a good audio clock and a processor clock for the sample rate converter AD1895A.
However, AD1955 has a problem with running off the 16.9344Mhz for SACD and CD non-upsampled as its internal PLL has problems locking to this (16.9344Mhz is 384FS. AD1955 has to convert this to 256FS, its internal clock).
Also if AD1955 is a bad choice, what would you recommend?
....And again the 33,8688M is NOT USED to clock the SRC (AD1895). It is used for 44.1k PCM and DSD.
It looks like you're not following what I am saying or you just don't want to. The 24,576M clocks the AD1895 SRC so whatever you are saying and what is posted on your friend's site is incorrect.
I would personally go for Crystal and even some Burr-Brown DACs before the AD1955. It's just me!
It specifically says that if your masterclock to the sample rate converter is less than 30Mhz, you can only operate up to 96Khz upsampling.
For 192Khz sample conversion, the only mode supported is the slave mode, and you need a masterclock > 30Mhz to do that.
In 963SA, the 24.576Mhz clock is used for
1. 96Khz upsampling master clock for AD1895sample rate convertor in Master mode.
2. Bit clock and LRCK generation in 192Khz mode (thru the syncronous counter IC, LVC161 I think.)
The 33.8688Mhz then is used as master clock for 192Khz mode only for AD1895A as it needs to operate in Slave mode and hence needs a master clock greater than 30Mhz for this.
In any case I have already measured the master clock pin of the AD1896A (mine is modded) of my 963SA in both 96Khz and 192Khz mode. I am correct.
For the ADI DACs, you are right about it though. The designer reports that it is so hard to sound-tune this IC especially with low budget given to him that for next generation players they would revert to crystal DACs, which is also lower in cost as they don't need expensive opamps for current-voltage conversion, being a voltage out DAC.
Why did the modder stick to op-amps for the analog stage ?
Wouldn't it be better to use a discrete output stage.
I suppose almost anybody would agree that this would lead to better results. (?)
....The clock CAN NOT be more than 30M. Since the AD1895/96 CAN NOT provide master clock in 192K mode (because it MUST work in "slave mode"), the Data Sheet calls for additional (optional) 24,567M clock to provide MCLK and LRCLK (divided) for the DAC. That is why the 963SA sounds worse in 192/24 mode. It is because the AD1985 switches to "slave mode" and the MCLK and LRCLK are provided by dividing the 24,567M clock.
I am not sure how to be more clear with you!? 33,8688 CAN NOT clock 192K as in slave mode as the AD1895/96 are SYNCHROUNOUS to the MCLK not asynchronous. You do the math, 33,8688 can not be divided by 128 in order to clock 192K.
128 x 192 is 24,576 it's THAT SIMPLE!
This is my last post here on this subject, but I highly recommend that you update your friend's site with the RIGHT information.
Alex, despite his sometimes loose interpretation of the forum rules regarding advertising and self-promotion, was at least never outright deceptive. This "customer" should get lost.
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