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Upsamplers, DACs, jitter, shakes and analogue withdrawals, this is it.

RE: Some kind questions about reclocking

The term "re-clocking" has been commonly used to describe decidedly different jitter reduction methods. Some DACs utilize a technology called Asynchronous-Sample-Rate-Conversion (ASRC), which alters the original sample amplitude values in order to effectively filter jitter from the incoming signal. This is more correctly called a re-sampling technology than it is re-clocking. ASRC does produce two independent clock domains, that of the incoming data signal and that of the re-sampled outgoing data signal. The outgoing data signal is usually timed by a fixed crystal controlled local (located within the DAC box) clock generator, which probably why it is often termed re-clocking.

There are other entirely different jitter reduction methods which do not alter the original sample values, yet still produce two nearly independent clock domains. These circuits typically utilize a specialized memory function known as an asynchronous FIFO, and some form of adjustable crystal controlled local clock generator. A DAC box might internally contain one or none of the above two highly effective jitter reduction technologies. In addition, there is yet another common meaning for the term re-clocking, wherein a new clock domain is not created. The data and any synchronously derived clock signals are simply re-aligned to whatever is the existing local clock domain.

In short, the term re-clocking doesn't by itself conclusively tell you whether effective jitter reduction is employed. In addition, we haven't even touched on the jitter that noise conduction across the transport to DAC digital signal interface can induce. A unusally well engineered DAC digital signal interface, such as Thorsten describes, can effectively cure all these problems, however, such is far from common.
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Ken Newton



Edits: 01/27/15 01/27/15 01/27/15 01/27/15 01/27/15 01/27/15 01/27/15

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