Digital Drive Upsamplers, DACs, jitter, shakes and analogue withdrawals, this is it.

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Connecting the Dots....

Posted by Todd Krieger (A) on September 22, 2006 at 19:51:05

In Reply to: I've posted links to papers about it multiple times: posted by Ted Smith on September 21, 2006 at 22:55:01:

The article does not state anything specific about *how* asynchronous sample-rate conversion (ASRC) rejects jitter.... Just the claim that because the output clock can be run independently, a steady rate of the output clock rejects jitter. The fallacy of the claim is explained as follows:

1. Per the functionality descriptions on the data sheets (see link, pages 16-18), an ASRC utilizes an extremely high rate of oversampling, to enable the output clock to send the closest approximated sample (from the intermediate oversampled signal) to the output. The internal sample rate may be high, but it is *not* infinite. And since the oversampled samples almost never exactly coincide with when the output clock triggers, jitter may actually be *introduced*. (All the output clock needs to be is more-precise than the ASRC's intermediate oversample rate.)

2. The premise that the output clock is inherently more-precise than the input clock. If the transport or the PLL buffer is already of high clock precision, such notion may not be true.

3. While the output clock may be precisely triggered, the intermediate oversampled signal, which the output takes samples from, is still timed to the *input* signal. Hence the oversampled signal also contains jitter from the input clock. So any jitter at the input and oversampled signal just gets passed-on to the output signal, regardless of the precision of the output clock. A timing error in the oversampled signal that is transferred to the output by a precise output clock will be seen as an *amplitude* error at the output. (Two otherwise-identical signals with one shifted in time will exhibit different amplitudes when sampled at the exact same instance.) So the jitter is transformed from frequency at the input to amplitude at the output, provided the output clock is of extreme time precision. If the output clock is not so precise, the output jitter will contain both frequency and amplitude components. So if anything, ASRC *introduces* amplitude jitter. AKA noise.

Since poor input clock precision (varying frequency) will likely show up as amplitude jitter using ASRC, this could explain why the DACs I've tried which had ASRC were seemingly more finicky with input/transports than DACs without ASRC. For the symptoms were not just degraded sound, but noise products as well.

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