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RE: Thanks for the good wishes.

I'm not sure we are communicating regarding what a FIFO can and can't do as regards removing "bits ain't bits". Or perhaps I'm off base and have been consistently missing something.

I'm not really concerned about the rate adaptation function of a DAC FIFO, as this can be dealt with by the clock architecture (e.g. slaving the transport to the DAC master clock). It looks like you've solved the problem for most interesting cases, as you can make the corner bandwith of your digital phase lock filter effectively zero once you've found a frequency setting that drains the buffer sufficiently slowly that no changes in rate are needed through the course of an entire track. The key to this, as it was obtaining stable jitter with the FDDI reclocking system, is to use buffer load state as well as rate differences as input to the feedback loop. My understanding is that you are doing this.

The other problem arises if you just take a jittery signal and reclock it with a clocked flip flop.(Here I'm talking about what is going on within a single clock domain.) The output transitions are supposed to follow the local clock, not the transition times of the input signal so long as the setup and hold times have been met. Of course they do not do so exactly, but the question is whether the net effect of the flip flop is to attenuate the variations. If so, then it should be possible to string a bunch of flip flops in series with appropriate clock scheme and achieve any desired degree of attenuation. I suspect the problem is that the output level of a gate depends slightly on all the input signals (e.g. the output of a NOR gate will be at a slightly lower level if all the input signals are true compared to just one) and the propagation delay through a gate depends on the level of the input signals. Perhaps your SPICE simulations are such as to demonstrate this phenomenon (or lack thereof).

Tony Lauck

"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar


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