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Hi Alan Just wanted to pass on some info that might point to bypassing the PLL when using I2S. When the Amenero or anything the outputs I2S receives a signal it uses its own I2S MCLK [master clock]for a PLL, therefore, if you used the Master7's PLL you will essentially be clocking the signal twice before it reaches the chips.
From Texas Instruments: [see pdf for full info]
In addition to I2S_CLK, I2S_WC, and I2S data lines, the Deserializer generates a Master I2S Clock (MCLK) using its internal I2S PLL.
http://www.ti.com/lit/an/snla221/snla221.pdf
Apparently this is why so many people at Headfi hear positive results when bypassing the PLL. See Link. http://www.head-fi.org/t/625793/audio-gd-master-7-discrete-fully-balanced-dac-pcm1704/2805 Basically you can think of the Amenero card in the Dac as a "Internal" USB to I2S converter as this is exactly what it does. Kingwa should actually by 'default' bypass the PLL for the DSP-1 when the Amenero is used...otherwise we have PLL x 2 of the data before it reaches the actual dac chips. Best jumper settings explanation, these settings have been confirmed via tests done by members over at Headfi. Kingwa does seem to contradict himself on the Audiogd web site maybe translation/confusion etc. http://www.basshead.club/audio-gear/master-11-info/
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