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Hi,
Today I tried the 100 Ohm, 1 mufarad loopfilter on pin # 20 of the CS8412 (instead of the factory recommended 1k, 0.05 mufarad). Courtesy of Monsan.
The sound was more at ease, but also dull. The air was gone!
Digital audio never ceases to amaze me. Anyone has the optimal loopfilter?
ELSO
Follow Ups:
Ya hoida me?Try a 470 or 500 ohm resistor in series with 0.22 microfarads; and up the loop to 3rd order by adding a 3300 picofarad cap from the loop filt pin directly to ground. This pin is *extremely* sensitive to noise pickup, keep lead lengths short. This attempts to keep adequate loop phase margin, maintaining settling time and avoiding peaking. Unfortunately there is no single best number here, and elsewhere for that matter.
Notice the vague square law correspondence here, the resistor is about half of the data book, and the cap is about 4x. Coincidence? Synchronicity? Just math...Within [or "below"] loop bandwidth the source phase noise dominates, and above it the local vco phase noise dominates. Hence the pll "tracks" the incoming frequency and artifacts with a settling time approx inverse to the loop bandwidth, so any peaking is to be avoided.
If one has the time to twizzle, a better solution [but not the one true way (tm)] is to place the master clock right at the DACs [fed by it's own regulated power supply] registering/reclocking the DACs and "slaving" the transport to that master clock, guaranteeing synchronicity [of the clocking type, not the cosmic type] and eliminating dependence on the pll/vco.
But, I admit, it is *fun* to meet the challenge and twizzle in an attempt to extract a clean enough clock.
Share and enjoy...
I've had this mod in for 2 days now and I must say that it did wonderful things for my Assemblage Dac 2.0. I've done quite a few mods to this unit, and optimizing the loop filter is one of the best so far. I'm using the unit with a Sonic Frontiers SFT-1 transport, supposed to be 10ps rms jitter on it's output. S/PDIF cable. There is more air, seperation and depth to the soundstage. Plus, things like bongo drums are much more realistic. Thanks for the tweak!
Regards,
RonS
Hey Ron, Steve, Elso et al [in random order]---thanks for the encouragement to dust off the old bag-o-tricks.
[soapbox mode]
It is a trip how many commercial products, including from well known names, so I won't single out any, are basically "data book" designs, with each subcircuit lifted [sometimes down to the exact part values] straight out of an app note; plug-n-play in pieces, with very little original thinking. In their defense, market forces do not always reward creativity, but jeesh, many of the latest whizzbang, state of the art, "gotta have it" products of the month are just hyped "quilts". Crystal DIR/SRC, Moto DSP, AD DAC, BB slopamps, stylish packaging, stir briefly, market well, and voila: breakthrough product.
[soapbox off]Share and enjoy...
Should the 3300pF cap go between the FLTR pin and ANGD pins directly? Pete Goudreau once recommended that I place a 1206 chip cap of 1nF soldered directly to these two pins on my Assemblage Dac 2.0.Also, what type of caps should be used for the .22 and 3300pF?
Regards,
RonS
Yes. Close to the pins is a good thing.Caps should be physically the smallest film caps you can find. Probably the type of film caps potted and encapsulated in rectangular plastic for radial through hole mounting would be a good choice, like with 0.1 or 0.2 inch lead spacing.
Some chip caps have mondo voltage and temperature coefficients. Even worse, piezoelectric...you can tap on them and hear the modulation effects. Really. Fun party tricks.Share and enjoy...
Hi, Wildmonkeysects,
I installed the components you suggested. Unbelievable. Glorious sound. Lot's of air, glare gone. How is this possible? About the math if the crossoverfrequency is 1/2piRC; your loopfilter is about 1/2 of the Crystal's frequency. Is the 3300pF doing the trick?
You last suggestion, placing the clock at the DAC looks even more promising. LC-Audio has a vague scheme of this on their website. My problem with this is that the masterclock of the CS8412 (MCK pin # 19) is a output and can not be used as a input. Or shall I use SCK pin # 12 as a input for the clock "format 11" ?
(BTW is "one true way" a registered trademark?)
Thanks again for the marvellous tweak.
ELSO
Well hey, thanks for the good news, glad to share.Yes, I found that reducing the loop corner/bandwidth/rolloff by half and adding the 3300pF cap was a [ not the one true ] sweet spot. The 84xx vco is probably not the cleanest one around, so there are diminishing returns when reducing the corner further. Also there are issues with loop stability and peaking. Have not twizzled the 8420, which includes a datasheet 1 kHz loop, and may well have a cleaner vco, but that is conjecture at this point. Anybody out there try one yet? Some revisions of the data sheet had the "extra" 3rd order loop filt cap, I seem to remember, but crystal has not revised the data sheets for the "older" chips, to my knowledge. They should. Probably the bigger factor is the 3300pF cap, as the loop filt pin will translate probably tens of nanovolts of noise into audible jitter.
One can "ignore" [ well almost, there will be a _small_ amount of jitter feedthrough between two oscillators sharing the same ground plane, but not enough to cause injection locking in this case ] the mclk generated by the 84xx DIR when placing the new master clock and register/reclocker at the DAC. The new master clock should be whatever the transport requires, probably 384 fs, maybe 256 fs. If 256 fs, you should see the "ignored" mclk pin of the 8412 in synch with the "new master". If 384 fs, the "ignored" mclk pin of the 8412 will be at 2/3 freq, but in synck, ie not wandering; and there should be sufficient setup and hold times avail at the reclocker/register next to the DAC. If not, invert the polarity of the new master clock at the transport to shift a half clock cycle.It's a mixed bag, genlocking, or master/slave clocking is more elegant, but more complex...
Now, there is one more way to "attack" the issue of correlated jitter that the SPDIF (sub)standard is soooo adept at generating that is not really commercially viable, but fair game in the arena of DIY:
A significant factor is the *low* frequency rolloff of the transmission medium shifting the level of the transition points. This is in some ways worse than jitter generated by high frequency roll off in the transmission medium, and contains components correlated down to the lowest frequencies of the audio data, including the envelope, which is typically subsonic ie the rhythum or phrasing of the audio.
Here is the fun part [well, to me at least]: by deliberately introducing a high pass / low roll off at least an order of magnitude higher than the highest anywhere else in the transmission chain, we can make it behave like a simple first order high pass, meaning critically damped, minimal undershoot. In other words, a differentiator. This is a big factor in keeping it from being commercially viable, preconceptions about noise sensitivity...maybe Peter Q who has both ears and b***s, and knows how to use them both would have success...
Anyhow, we have essentially removed sensitivity to low frequency roll offs in the transmission chain by transmogrifying the SPDIF [ also applies to AES with higher voltage levels ] waveform suchly: what was a positive going transition from -0.25V to +0.25V is now a positive spike with a clean decay lasting 10s of nanoseconds, and conversely what was a negative transition from +0.25V to -0.25V is now a negative spike with a similarly clean decay "upward" lasting 10s of nanoseconds. Then, we drive two fast comparitors set as a window comparitor who drive a set/reset flipflop, or a dflop via the set and reset pins producing a clean zero to vdd SPDIF signal which can directly [ no coupling caps needed ] drive the 84xx inputs from q and qbar.I need to dust off and reverse engineer the part values I used [am I the only one who is lax about taking notes...] and _will_ post a schematic, unfortunately in about a month or so after work settles down a bit.
The bad news is that there is sensitivity to radiated noise, ie AC motor start surges, piezo stove starters will cause some bits to be dropped, and may cause secondary low frequency loops to slip for a moment. The good news is that it removes yet another layer of grunge and makes it all more solid and tight with more defined space around musical events.
The golden handcuffs call, back to work.
Share and enjoy...
Hi Wildmonkeysects,
Thanks for the reply. Yes Crystal has even a application note (#159) about the loop filter optimization for the CS8415A, 8429 and 8427 but not for the CS8412!As regards the "stand alone" operation of the CS8412: What I was hoping for was NOT to extract the bitclock SCK and FSYNC from the datastream. But I am afraid only the CS8411 is suitable for that kind of operation. {If I understand the datasheet correctly. Apparently these Crystal dataheets are written by a individual coming from Mars or other strange planet} I don't like the idea of reclocking the incoming DATA; I feel this is wishful thinking. All in one the CS8412 seems to be predestined of working on a SPDIF or AES/EBU datastream.
You raise a interesting point in addressing the low frequency rollof of the interface... Well I have done some experiments here by driving directly the 75 Ohm cable. The data come from the Sony CXD2500Q pin 60 ; than go through one inverter of 74HC04U and splits into two other inverters; one of them driving the Toslink output the other driving the base of a 2N2369A transistor. The transistor's collector connected to +5V, the emittor coupled with a 75 Ohm emittor resistor to the core of the coax cable(75 Ohm). When the cable is connected to the DAC where it is terminated with 75 Ohm to ground the transistor starts working. [Idea borrowed from Horowitz, the Art of Electr. and Analog Devices] The data signal looks very nice on the scope using a HF probe. ["Normal" probes are useless with these high frequencies. The HF probe is nothing more or less than a piece double terminated coax cable] In spite of this effort I hear no difference between coax input and Toslink input and that is cursing and swearing in the church...or shall I say heresy on these pages?
In Germany is a guy Stefan Craemer who has a complete and expensive interface system. He holds even a patent on it. See the link. My scheme looks ridiculously simple compared to that.
Looking forward to your next post.
Cordially,
ELSO
Hmm, I couldn't quite fully translate the data sheets and tech support either; it appears the word select [l/r] output is derived from the preamble so supposedly has less correlated jitter; however, as we have found it is generally better to reclock the with the 256 fs externally.I have extracted a 2 fs signal from the SPDIF/AES preamble with couple of politically incorrect monostables. This might be useful for reclocking/registering a DAC that updates with a latch enable transition such as the AD 1865, 1862, or BB 63; but is mostly useless
with the type of DAC that updates on a clock cycle after a latch enable transition like the BB 1700, 1702, 1704. The 1541 can be either depending on the input mode selected, but at 1x fed by the 8412 in 1^2s mode, it is in the latter category.After mulling a bit [pun], maybe the "old" 8412 is not ready for pasture, or the glue factory just yet. Especially with TSE so rampant. The "newer" ones that are 96 kHz ready have the laws of physics working against them: a higher frequency range vco has a higher K sub o which means the vco control pin, like the loop filt pin, is _more_ sensitive, not just to intended signal, but also noise. Generally, the narrower the band of a vco, the lower the phase noise and jitter. Granted, there are heoric engineering feats to make up for handicaps, but the laws of physics do in a Zen like way point towards lower bandwidth vcos as the way to go.
Hey, the trick of 75 ohm terminating/matching the cable and using it as a DC path is a totally kewl one that does not strictly follow standards, but is fair game in DIY land. A tradeoff is you give up ground isolation that transmormer coupling provides, but quite likely you more than make up for that with less interface high pass [ low freq rolloff ] issues.
One of these days when in the mood for a flame war we should start a string along the theme of perceptual significance.
Share and enjoy...
Hi WMS,any idea how hard it is to get the PCM63 running without a DF to expand the data stream to 20 bits? I tried a while ago, and ended up way too many logic chips, I'm sure (just a pencil and paper design). Is there an easy way? Am glad I'n not the only one who finds the CS data sheets gobbldygook.
Dan
Here's hoping TI keeps it in production. The separate offset current pin enabling a single ended looped cascode I/V would be missed.Do you mean:
16bit 1x data, fed directly from a sony cdx25xx, or cs 84xx?
20 bit 1x data from cs 84xx?
Separate l/r 1x data from elsewhere like a xilinx or dsp?
The BB 63 data sheet is not clear whether or not the internal registers are flushed _and_ reset with each l/e negative transition. One would presume that, unlike with the BB 1700/1702/1704, based on the ability to do stopped clock mode(s), it would.
Anybody out there done a test to see if the unused bits powerup to zero and/or reset to zero? Knowing this would greatly simplify 1x apps.
Share and enjoy...
Great stuff, Elso.I'm going to be doing the MSB adjust via your curcuit that you kindly sent me, very soon.
Please keep it coming!
I'm like Rosie O'Donnell at an all you can eat smorgasborg!
Cheers,
-Steve
Er, did I blink and miss the MSB twizzle?
Other than bypassing all pins associated with with MSB ajdust?WMS
Hi Wildmonkeysects,
Steve described my little circuit in very kind words. It is a MSB adjustment rig for R-series DACs like AD 1851, AD1865 (used by Audionote) I am still thinking about a circuit for the Philips TDA1541. Maybe I must inject a smal current instead of a voltage here.
If you are interested in the circuit -it is a 4 pole Butterworth low-pass filter with gain; crossing over at 10k Hz- I can send you it by e-mail. It will be in the Designworkslite format (program obtainable free of charge) or in the Boardmaker1 format(not free). I will study your other post tomorrow with a clearer head.
Also on the schedule is a comparison of the TDA1541 with the AD1851 soundlike.
Best regards, good night,
ELSO
No, you didn't miss it. Wasn't posted.Elso sent me a few emails details his experiences and sucess adding a MSB adjust. He designed a LP filter curcuit optimized to view a -60dB 300Hz signal (without out of band garbage).
Really slick and practical. I'll be putting it to good use in the near future.
Thanks again Elso, and wildmonkeysects.
Cheers,
-Steve
Mr. Wildmonkeysects,That's some high octane fuel you're burning!
P-L-E-A-S-E keep it coming!
Cheers,
-Steve
> the loop filt pin will translate probably tens of nanovolts of noise > into audible jitter.Should read tens of microvolts.
When I retire, I's gonna hire me a proofreader.
I replaced the stock Crystal suggested implementation with Wildmonkeysects' filter.Highly recommended.
Thanks again and keep the info comming, dude!
Cheers,
-Steve
nt
HI,
Thanks. I will try that and report back.
ELSO
nt
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